Posted on Jun 28, 2012 5751
without significant added complexity, and a natural tendency to run away under no-load (high Q) conditions. The 20-kHz control circuit (see Fig. 2) overcomes these shortcomings hy feeding back into the asymmetrical thyristor trigger pulse generators (see Fig. 3) signals that simultaneously shut the inverter down, when its output voltage exceeds a preset threshold, then time-ratio modulates the output. This feedback is accomplished with full galvanic isolation between input and output thanks to an HllL opto-Schmitt coupler. The fundamental 20-kHz gate firing pulses are generated by a PUT relaxation oscillator Ql.
The pulses are then amplified by transistors Q2 and Q3. The 20-kHz sinusoidal load current flowing in the primary of the output transformer is then detected hy current transformer CTl, with op amp Al converting the sine wave into a square wave, whose transitions coincide with the load current zero points. Consequently, each time the output current changes, phase Al also changes state and, via transistor Q4, either connects the thyristor gate to a -8 V de supply for minimum gate assisted tnm-off time and highest reapplied dV/dt capability or disables this supply to prepare the thyristor for subsequent firiog. Modulation intelligence is coupled into this same HllL through two additional PUTs, Q6 and Q7, Q6 oscillates at a fixed 1.25 kHz, which establishes the modulation frequency. The duty cycle is determined by a second oscillator, Q7, whose conduction state, on or off, establishes or removes current from the HllL diode. With a fundamental inverter frequency of 20kHz and a modulation frequency of 1.25 kHz. Where PM ~ 100% continuous output power. Minimum power is one cycle of 20kHz (50 p.s) in the 1.25- kHz modulation frame (800 p.s), that is, 6.25% PM.