Programmable Sound Generator

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Category: Audio Circuits / Musical & effects
This circuit is also crossed to: PIC Microcontroller , Audio Oscillators
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The AY-3-8910/8912 is a register oriented Programmable Sound Generator (PSG). Communication between the processor and the PSG is based on the concept of memory-mapped I/O. Control commands are issued to the PSG by writing to 16 memory-mapped registers. Each of the 16 registers within the PSG is also readable so that the microprocessor can determine, as necessary, present states or stored data values. All functions of the PSG are controlled through its 16 registers which once programmed, generate and sustain thesounds, thus freeing the system processor for other tasks.Conditioning of the Register Address Latch/Decoder and the Bidirectional Buffers to recognize the bus function required (inactive, latch address, write data, or read data) is accomplished by the Bus Control Decode block. The function of each of the 16 PSG registers and the data flow of each register’s contents are shown in context in Fig. 2 and explained in detail in Section 3, Operation”. For reference purposes, the Register Array details are reproduced in Fig. 3. 2.1.2 SOUND GENERATING BLOCKS The basic blocks in the PSG which produce the programmed sounds include: Tone Generators Noise Generator Mixers Amplitude Control Envelope Generator D/A Converters produce the basic square wave tone frequencies for each channel (A,B,C) produces a frequency modulated pseudo random pulse width square wave output. combine the outputs of the Tone Generators and the Noise Generator. One for each channel (A,B,C). provides the D/A Converters with either a fixed or variable amplitude pattern. The fixed amplitude is under‘ direct ‘CPU control; the variable amplitude is accomplished by using the output of the Envelope Generator. produces an envelope pattern which can be used to amplitude modulate the output of each Mixer. the three D/A Converters each produce up to a 16 level output signal as determined by the Amplitude Control. 2.1.3 I/O PORTS Two additional blocks are shown in the PSG Block Diagram which have nothing directly to do with the production of sound-these are the two I/O Ports (A and B). Since virtually all uses of microprocessor-based sound. would require interfacing between the outside world and the processor, this facility has been included in the PSG. Data to/from the CPU bus may be read/written to either of two 8-bit I/O Ports without affecting any other function of the PSG. The I/O Ports are TTL-compatible and are provided with internal pull-ups on each pin. Both Ports are available on the AY-3-8910; only I/O Port A is available on the AY-3-8912. Since the PSG functions are controlled by commands from the Bus Timing system processor, the common data/address bus (DA7--DAO) requires definition as to its function at any particular time. This is accomplished by the processor issuing bus control signals, previously described, defining the state of the bus; the PSG then decodes these signals to perform the requested task. The conditioning of these bus control signals by the processor is the same as if the processor were interacting with RAM: (1) the processor outputs a memory address; and (2) the processor either outputs or inputs data to/from the memory. The memory” in this case is the PSG’s array of 16 read/write control registers. The timing relationships in issuing the bus control signals relative to the data or address signals on the bus are reviewed in general in the following section, and in detail in Section 7, Electrical Specifications. visit page.

Conditioning of the Register Address Latch/Decoder and the Bidirectional Buffers to recognize the bus function required (inactive, latch address, write data, or read data) is accomplished by the Bus Control Decode block. The function of each of the 16 PSG registers and the data flow of each register’s contents are shown in context in Fig. 2 and explained in detail in Section 3, Operation”. For reference purposes, the Register Array details are reproduced in Fig. 3. 2.1.2 SOUND GENERATING BLOCKS The basic blocks in the PSG which produce the programmed sounds include: Tone Generators Noise Generator Mixers Amplitude Control Envelope Generator D/A Converters produce the basic square wave tone frequencies for each channel (A,B,C) produces a frequency modulated pseudo random pulse width square wave output. combine the outputs of the Tone Generators and the Noise Generator. One for each channel (A,B,C). provides the D/A Converters with either a fixed or variable amplitude pattern. The fixed amplitude is under‘ direct ‘CPU control; the variable amplitude is accomplished by using the output of the Envelope Generator. produces an envelope pattern which can be used to amplitude modulate the output of each Mixer. the three D/A Converters each produce up to a 16 level output signal as determined by the Amplitude Control. 2.1.3 I/O PORTS Two additional blocks are shown in the PSG Block Diagram which have nothing directly to do with the production of sound-these are the two I/O Ports (A and B). Since virtually all uses of microprocessor-based sound. would require interfacing between the outside world and the processor, this facility has been included in the PSG. Data to/from the CPU bus may be read/written to either of two 8-bit I/O Ports without affecting any other function of the PSG. The I/O Ports are TTL-compatible and are provided with internal pull-ups on each pin. Both Ports are available on the AY-3-8910; only I/O Port A is available on the AY-3-8912. Since the PSG functions are controlled by commands from the Bus Timing system processor, the common data/address bus (DA7--DAO) requires definition as to its function at any particular time. This is accomplished by the processor issuing bus control signals, previously described, defining the state of the bus; the PSG then decodes these signals to perform the requested task. The conditioning of these bus control signals by the processor is the same as if the processor were interacting with RAM: (1) the processor outputs a memory address; and (2) the processor either outputs or inputs data to/from the memory. The memory” in this case is the PSG’s array of 16 read/write control registers. The timing relationships in issuing the bus control signals relative to the data or address signals on the bus are reviewed in general in the following section, and in detail in Section 7, Electrical Specifications. http://users.rcn.com/carlott/ay3-8910.pdf

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