Delay Circuits

The Sallen-Key realization of a 5.25-MHz, three-pole Butterworth filter has a gain of 2V/V and can drive 75Ω back-terminated coax with an overall gain of 1 (Figure 1). Used to reconstruct component-video (Y, Pb, Pr) and RGB signals, this filter has an insertion loss greater than 20 db at 13.5 MHz and greater than 40 db at 27 MHz (Figure 2). Like the antialiasing filter before an ADC, this filter removes the higher frequency replicas of a signal following a DAC. To preserve quality in the video waveform, you should minimize group-delay variations in the filter and any group-delay differential between filters.

Many designers use small pulse generators to delay signals, open timing windows, drive sample/hold circuits, and other functions. Though the hardware implementation of these generators does not pose any problems, the lack of dedicated circuitry sometimes puzzles the Spice simulation of the system. A common approach to this problem is to implement a time constant involving a resistor, a capacitor, and a comparator. Unfortunately, each time you need a time constant, you must recalculate the resistor value, the capacitor value, or both.

Generating complementary clock signals in a Spice simulation is an easy task. However, this task gets much harder if you need to introduce some dead time into the signals. This difficulty is especially true when you're dealing with a variable-pulse-width-modulated switching cycle. In fact, you need to insert a dead-time interval between the switching of any two power devices in series, such as bridge or half-bridge designs that use MOSFETs and switch-mode power supplies and that implement synchronous rectification.

Timing delays are undesirable in most digital circuits. However, in some cases, delays can be useful—to deal with a µP-speed-compatibility issue, for example. The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler. Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock. Using a more precise delay line, the circuit can output a triple clock (Figure 1b).

Phone calls over satellite circuits experience a Ό-sec transmission delay in each direction. The low-cost circuit (around $20) in Fig 1a simulates this delay and provides hooks for inserting noise, echo, and other impairments. Designers debugging modems, fax machines, and other communication equipment can use this circuit to troubleshoot handshake timing and connection problems caused by transmission delays.

This is an unusual design in that it uses plain metal gate CMOS logic instead of the usual PIC or a custom chip. The 22uF capacitor charges up during one half of the ac cycle, and supplies trigger current to the triac on both halves.

In a CCD (charge-coupled device), packets of charges shift across the array. The transistor array, also called a bucket-brigade shift register, receives drive from a dual-phase clock signal. Dual-phase clock signals comprise two synchronized clock signals that are 180° out of phase. High peak-output-current CCD drivers can buffer the logic-level clock signals and turn them into high-voltage and high-peak-current signals to drive the heavily capacitive gates of the many CCD transistors.

For numerous applications, flat group delay (linear phase) is necessary to maintain system performance. The common group-delay equalizer of Fig 1a has unity gain and is a popular way to equalize data filters or alias filters when phase compensation is necessary. The alternative equalizer of Fig 1b, however, can provide a gain greater than one for systems that require additional gain (and when providing that gain elsewhere is impossible or impractical).

The power line fluctuations and cut-offs cause damages to electrical appliances connected to the line. It is more serious in the case of domestic appliances like fridge and air conditioners. If a fridge is operated on low voltage, excessive current flows through the motor, which heats up, and get damaged. The under/over voltage protection circuit with time delay presented here is a low cost and reliable circuit for protecting such equipments from damages. Whenever the power line is switched on it gets connected to the appliance only after a delay of a fixed time.

Voltage variations and power cuts adversely affect various equip- ment such as TVs, VCRs, music systems and refrigerators. This simple circuit will protect the costly equipment from high as well as low voltages and the voltage surges (when power resumes). It also gives a melodious tune when mains power resumes. When mains voltage is normal, the DC voltage at the cathode of zener diode D4 is less then 5.6V. As a result transistor T1 is in ‘off’ state. The DC voltage at the cathode of zener diode D5 is greater than 5.6V and as a result transistor T2 is in ‘on’ state. Consequently, relay RL1 gets energised, which is indicated by lighting up of green LED.

Here's a power-on time delay relay circuit that takes advantage of the emitter/base breakdown voltage of an ordinary bi-polar transistor. The reverse connected emitter/base junction of a 2N3904 transistor is used as an 8 volt zener diode which creates a higher turn-on voltage for the Darlington connected transistor pair. Most any bi-polar transistor may be used, but the zener voltage will vary from about 6 to 9 volts depending on the particular transistor used.

This circuit waits for a set time and then activates a relay. With the cap that is in the schematic you will get about a 6 sec delay till power on. You can change the cap in this circuit to 470uF for about a 20 sec delay.

When activated by pressing a button, this time delay relay will activate a load after a specified amount of time. This time is adjustable to whatever you want simply by changing the value of a resistor and/or capacitor. The current capacity of the circuit is only limited by what kind of relay you decide to use.

A time delay relay is a relay that stays on for a certain amount of time once activated. This time delay relay is made up of a simple adjustable timer circuit which controls the actual relay. The time is adjustable from 0 to about 20 seconds with the parts specified. The current capacity of the circuit is only limited by what kind of relay you decide to use.

The Saver V5.0 runs simple clock emulation program, turns a night light on and off with preset time, say 19:00 to 22:00 everyday. The design features low cost, easy installation, no battery backup and no EMI. The AT89C2051 uses external oscillator generated by schmitt trigger gate CD4093, ~680kHz. Reference frequency was derived from 50Hz main line.

This page features a circuit that has twenty open collector outputs that turn on one at a time in a continuous sequential manner. The circuit make use of the 74LSxx family of TTL integrated logic devices. The circuits are designed to drive light emitting diodes or low current, low voltage incandescent lights but can also drive other loads of up to 80 milliamps.

This timer was designed for people wanting to get tanned but at the same time wishing to avoid an excessive exposure to sunlight. A Rotary Switch sets the timer according to six classified Photo-types .

The purpose of this circuit is to power a lamp or other appliance for a given time (30 minutes in this case), and then to turn it off. It is useful when reading at bed by night, turning off the bedside lamp automatically in case the reader falls asleep... 30 minutes operation Blinking LED signals 6 last minutes before turn-off

This software functions as a long period astable mutivibrator. The mark and space period can be set from 1 second up to a maximum 65535 seconds (18h12m15s). Using the internal 4Mhz RC oscillator delays with an accuracy of 99% or better can be achieved The code also implements an edge triggered reset and an active low hold function. The reset edge can be configured for rising or falling edge. The hold function is active low and stretches the timed period for as long as the hold input is held low. In addition to this up to 128 mark/space time pairs can be used which are executed sequentially allowing complex pulse trains to be generated.

A rising edge on the Trigger input starts a delay timer. At the end of the delay period Output 1 goes high and a second delay timer is started. At the end of the second delay Output 2 goes high. This is repeated for Outputs 3 and 4. The result is four outputs that go high in sequence with user defined delays between each one. Once Output 4 has gone high, a high level on the Reset input causes all four outputs to clear and the program goes back to the initial state waiting for a rising edge on the trigger input.