Delay Circuits

Timing delays are undesirable in most digital circuits. However, in some cases, delays can be usefulto deal with a µP-speed-compatibility issue, for example. The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler. Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock. Using a more precise delay line, the circuit can output a triple clock (Figure 1b)...

This is an unusual design in that it uses plain metal gate CMOS logic instead of the usual PIC or a custom chip. The 22uF capacitor charges up during one half of the ac cycle, and supplies trigger current to the triac on both halves...

In a CCD (charge-coupled device), packets of charges shift across the array. The transistor array, also called a bucket-brigade shift register, receives drive from a dual-phase clock signal. Dual-phase clock signals comprise two synchronized clock signals that are 180° out of phase. High peak-output-current CCD drivers can buffer the logic-level clock signals and turn them into high-voltage and high-peak-current signals to drive the heavily capacitive gates of the many CCD transistors...

For numerous applications, flat group delay (linear phase) is necessary to maintain system performance. The common group-delay equalizer of Fig 1a has unity gain and is a popular way to equalize data filters or alias filters when phase compensation is necessary. The alternative equalizer of Fig 1b, however, can provide a gain greater than one for systems that require additional gain (and when providing that gain elsewhere is impossible or impractical)...

Voltage variations and power cuts adversely affect various equip- ment such as TVs, VCRs, music systems and refrigerators. This simple circuit will protect the costly equipment from high as well as low voltages and the voltage surges (when power resumes). It also gives a melodious tune when mains power resumes. When mains voltage is normal, the DC voltage at the cathode of zener diode D4 is less then 5.6V. As a result transistor T1 is in off state. The DC voltage at the cathode of zener diode D5 is greater than 5.6V and as a result transistor T2 is in on state. Consequently, relay RL1 gets energised, which is indicated by lighting up of green LED...

Here`s a power-on time delay relay circuit that takes advantage of the emitter/base breakdown voltage of an ordinary bi-polar transistor. The reverse connected emitter/base junction of a 2N3904 transistor is used as an 8 volt zener diode which creates a higher turn-on voltage for the Darlington connected transistor pair. Most any bi-polar transistor may be used, but the zener voltage will vary from about 6 to 9 volts depending on the particular transistor used...

This circuit waits for a set time and then activates a relay. With the cap that is in the schematic you will get about a 6 sec delay till power on. You can change the cap in this circuit to 470uF for about a 20 sec delay...

When activated by pressing a button, this time delay relay will activate a load after a specified amount of time. This time is adjustable to whatever you want simply by changing the value of a resistor and/or capacitor. The current capacity of the circuit is only limited by what kind of relay you decide to use...

A time delay relay is a relay that stays on for a certain amount of time once activated. This time delay relay is made up of a simple adjustable timer circuit which controls the actual relay. The time is adjustable from 0 to about 20 seconds with the parts specified. The current capacity of the circuit is only limited by what kind of relay you decide to use...