Thyristor zero trigger circuit output waveform is a sine wave, it will not produce as phase-shift trigger circuit as electromagnetic interference.
This is a zero trigger thyristor power adjustment of the basic circuit. The figure, the regulator vs plays clamping action and to provide access to the charging capacitor Ci; VD role is to prevent the negative half cycle of the power supply capacitor Cz reverse charge; resistance Rz and R4 are current limiting resistor to limit the control current. Figure, power outage time digging 1 and 2 depending on the time bar switch length (or control contact) SA opening and closing time. That load power by the SA control.