Voltage controlled gain amplifier LM307

As shown for the voltage-controlled gain amplifier. Use FET gate voltage and the drain - source resistance between RSD to approximate logarithmic relationship may constitute a
Voltage controlled gain amplifier LM307 - schematic

voltage-controlled gain amplifier. The integrated circuit chip LM307 amplifier circuit, take the inverting input. Figure (a) shows that, RSD and R1 form a voltage divider (for Vi partial pressure). 4 1N914 diode voltage drop and the voltage drop across the resistor R5 and the gate voltage VG is equal to the FET. The VG control voltage VC is nonlinear, but the amount of attenuation control voltage VC and the amplifier gain corresponding relationship as shown in (b) below. Figure (b) shows that the larger the control voltage VC, the smaller the amount of attenuation of the amplifier gain, that is, when VC 7V, amplifier gain maximum (minimum attenuation); when VC 0V, the maximum amount of attenuation of the amplifier gain ( the minimum gain). Figure (a) shows the maximum and minimum gain of the circuit is: When VC 7v, the maximum gain is: Avmax -R3/(R1 + R2). When VC 0V, the minimum gain is: Avmin -R3/(R2 // RSD + R1). The circuits upper cutoff frequency depends on the low-pass filter between R1 and FET capacitance posed. For the FIG. (A) component parameters as shown in its worst upper cut-off frequency up to 1.8MHz, the value in the case of VC 7V measured (ie, the maximum gain of the circuit is measured). The main parameters (typ) LM307 integrated chip

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