Latching is obtained by storing the gate trigger energy from the preceding half cycle in the capacitors. Powe
r must be interrupted for more than one full cycle of the line to ensure turn-off. Resistor R and capacitor C are chosen to minimize dissipation, while assuring triggering of the respective SCRs for each cycle. A pulse of current, over 10 ms duration into the H11C4 IRED, ensures triggering the latching relay into conduction.