Digital-tach-dwell-meter

  
The heart of the circuit is ICZ, a 4046 micropower phase-locked loop (PLL). The incoming signals are fed to the PLL after being buffered by IC1a and its associated components. The frequency of the incoming signal is multiplied by either 90, 60, or 45, depending on the setting of the cylinder select switch, SZ. That switch selects the proper output from counters IC3 and IC4, which are set to divide the output frequency of the PLL by those amounts, and then send the divided output back to the comparator to the PLL to keep it locked on to the input signal. The phase pulses output at pin 4 of ICZ, then go through an AND gate IC5d-which only passes the signals if the PLL is locked on to an input signal, preventing stray readingsand then to the input of IC6.
Digital-tach-dwell-meter - schematic

When in the tach mode, IC6 counts the number of pulses present at pin 12, during the timing interval generated by IC8 and the associated circuitry of IClb. Because of the varied multiplication rate for the different cylinder selections-90, 60, and 45 for 4, 6, and 8 cylinders, respectively, the time interval is always constant at 113 of a second. The time interval is adjusted with R9, a 500K! l potentiometer; it is the only adjustment in the circuit. In the high-tach (TACH 1 or x 100) range of 0-9990 rpm, the output oUCZ is routed by switches S1a and S3 through IC7, a divide-by-ten counter, which increases the count range tenfold. In the low-tach (TACH 2 or x 10) range of 0-999 rpm, the counter is bypassed.




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