2 GHz CMOS Voltage-Controlled Oscillator with Optimal Design of Phase Noise and Power Dissipation

Posted on Feb 6, 2014

The oscillator is designed to tune from 1. 8 GHz to 2 GHz for typical cellular telephony applications. An extended tuning range can be obtained by adjusting the ratio between the varactor capacitance and fixed capacitance in the tank. PMOSFETs are employed in the design due to their low 1/f noise characteristics, critical for minimizing close-in ph

2 GHz CMOS Voltage-Controlled Oscillator with Optimal Design of Phase Noise and Power Dissipation
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ase noise. The oscillator LC tank is composed of a single three-turn center-tapped differential inductor [17] with an inner radius of 150 m and trace width and spacing of 30 m and 3 m, respectively, and a capacitive network of MOS varactors and MIM capacitors. The inductor exhibits a differential inductance of 4. 6 nH with a Q of 15 at 2 GHz. P-channel MOS capacitors are used as varactors for tuning the oscillator frequency. The varactors are biased in the depletion region to achieve a capacitance range from 2. 4 pF to 1. 6 pF at VGB of -0. 4V and -1. 1V, respectively, while maintaining a high quality factor of over 30. To obtain the desired VCO frequency tuning range, additional high-Q MIM capacitors of 225 fF are included in the tank. Another parallel LC tank consisting of Lfilter and Cfilter, tuned to twice of the operating frequency (2f0 = 3. 8 GHz), is employed to suppress the up-conversion mechanism of the baseband noise from the biasing transistor (M3), as proposed in [6], to minimize phase noise at low offset frequencies near the carrier. Properly designing the differential pair transistors` mode of operation is crucial for achieving a low phase noise performance at minimal core bias current. Leeson`s phase noise equation [18] suggests that low phase noise performance can be achieved by enhancing the RF power or oscillation signal amplitude through increasing the oscillator core bias current. However, designs aiming...

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