24hr clock using logic ics

  
Inside:
Repository
The count advances as the clock input becomes high (on the rising-edge). Each output Q0-Q9 goes high in turn as counting advances. For some functions (such as flash sequences) outputs may be combined using diodes. The reset input should be low (0V) for normal operation (counting 0-9). When high it resets the count to zero (Q0 high). This can be do
24hr clock using logic ics - schematic

ne manually with a switch between reset and +Vs and a 10k resistor between reset and 0V. Counting to less than 9 is achieved by connecting the relevant output (Q0-Q9) to reset, for example to count 0, 1, 2, 3 connect Q4 to reset. The disable input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant. The G·10 output is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It can be used to drive the clock input of another 4017 (to count the tens). The count advances as the clock input becomes high (on the rising-edge). The outputs a-g go high to light the appropriate segments of a common-cathode 7-segment display as the count advances. The maximum output current is about 1mA with a 4. 5V supply and 4mA with a 9V supply. This is sufficient to directly drive many 7-segment LED displays. The table below shows the segment sequence in detail. The disable clock input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant. The enable display input should be high (+Vs) for normal operation. When low it makes outputs a-g low, giving a blank display. The enable out follows this input but with a brief delay. The G·10 output (h in table) is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It...



Leave Comment

characters left:

New Circuits

.