8051 Development System Circuit Board 3

  
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This schematic is provided in the hope that it will be useful, but without any warranty, not even a warranty of merchantability or fitness for a particular purpose. The address bus in this schematic is connected in an unusual way, which is optimized for simpler point-to-point wiring and board layout. For anyone building the board using wire-wrap o
8051 Development System Circuit Board 3 - schematic

r hand soldered point to point construction, this wiring scheme makes for much less clutter in the wiring if the chips are positioned similarly to the layout on the printed circuit board. This unusual address bus wiring works. The 74HC373 chip (U2) is 8 identical flip-flops, so it does not matter which one is used for each line. On the RAM (U3) and Flash ROM (U4) chips, all data that is stored in these chips is written by the 87C52 chip (U1), so it does not matter which physical location within the chip is mapped into each location within the CPU`s address space, because each read from these chips will return the same data that was written from a previous write. Some readers have felt that it`s "just not natural" to connect any other way than P0. 0-D0-Q0-A0, P0. 1-D1-Q1-A1, and so on, but it does indeed work. For a historic example, Woz used a very creative address bus connection scheme in the Apple ][ to automatically do DRAM refresh with his video refresh reads. Because he arranged the address pins a certain unusual way, every video mode accessed each DRAM row several times per video refresh, so he didn`t need to add the cost and space of the usual DRAM refresh circuits (he interleaved video and cpu memory access, since the 6502 spends half its time not fetching anything). It works, and Apple sold millions of them! The MAX232 chip (U9) is shown with C3, C4, C5, and C6 as 1 µF, but the board is usually built with 10 µF...



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