Analog 5Gb/s Clock-and-Data Recovery Circuit

A clock-and-data recovery (CDR) circuit is used to both recover the clock from a transmitted data stream and re-time that data with the recovered clock. Such circuits are typically placed at the front-end of receiver chips to recover the clock from data sent from a transmitter chip across a backplane or other channel. This project presents a fully
Analog 5Gb/s Clock-and-Data Recovery Circuit - schematic

-analog CDR that uses phase interpolation to adjust the phase of a locally generated 5GHz clock to align with the phase of an incoming 5Gb/s data stream. A binary phase detector performs two functions: (1) re-times the incoming data stream with the recovered clock; (2) compares the phase of the data and recovered clock, generating differential up and down pulses. These pulses are converted to DC values by a differential charge pump and loop filter. A voltage-to-current converter converts these voltages to differential currents that fed to a phase interpolator (PI) controller. The PI controller determines the smaller of the two currents using a comparator and generates four steering currents. These currents are fed to two phase interpolators and control the degree of interpolation applied to the four-phase (i. e. , differential in-phase and quadrature) locally-generated 5GHz clock. These phase-adjusted clocks are then buffered and fed back to the phase detector as the 5GHz recovered clocks, thereby completing the feedback loop. A block diagram of the CDR is shown in Fig. 1. By adjusting only the local clock`s phase (and not its frequency), all data channels in a receiver can share a single PLL, thus significantly reducing area and power consumption. The phase detector, shown in Fig. 2 samples the data using three parallel master-slave flip-flops constructed with current-mode logic (CML) latches, one of which is shown in Fig....

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