Bus masters diagram

It is possible to add bus masters to the system, but a different bus architecture would be required, since the Integrator/CP uses the AHB-Lite bus protocol, which allows only one bus master (the ARM CPU core). One way to add bus masters in a Logic Tile would be to instantiate a bridge in the IM-LT3 FPGA, and splitting the Z[127:0] bus at the IM-LT3.
Bus masters diagram - schematic

The custom masters (and slaves) could then exist on the upper segment of this bus, and the Integrator/CP's AHB-Lite System bus would continue to exist on the lower segment of the bus.

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