DDR SDRAM and the TM-4

Posted on Feb 5, 2014

DDR SDRAM is a dynamic ram standard that is designed to provide high memory depth and bandwidth. This section will provide the basic DDR SDRAM background necessary to effectively use the TM-4`s memory subsystem. In particular the memory organization will be presented, followed by a description of how both reads and writes are performed. In a DDR S

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DRAM dimm there are usually two memory chips connected in parallel, with only their chip enable signals being unique. This configuration allows the two chips to share address and data lines. By selectively asserting only one chip enable single at a time, this configuration allows twice the memory depth compared with only a signal chip. The highest level of the memory addressing hierarchy controls these chip enable signals. This addressing level is called the chip selects. The remaining three addressing levels all take place within a single memory chip. Figure 1 shows a simplified block diagram of the internals of a DDR SDRAM memory chip. At the core of the memory chip are four 2D memory array banks. Each of these memory banks is addressed by both a row and column address. To understand why this memory structure was selected it is necessary to first understand the process of reading from one of the 2D memory arrays. To read from the 2D memory array involves several steps. The first step involves selecting which row in the memory array to address. This is accomplished by issuing an ACTIVE command to the memory. This results in the memory array outputing an entire row of data via the sense amplifiers, shown in figure 1. At this point the memory chip is ready to accept read commands. These read commands include a column address, which is decoded and used to select which piece of data, currently outputted by the sense...

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