DECL Documentation

Posted on Feb 6, 2014

The following describes the design, construction, operation and use of the DECL (Decade PLL) module. The module has both a Phase Locked Loop (PLL) frequency multiplier and a frequency divider to produce various output frequencies that are based on an input reference frequency. The primary use of the module is to condition the ten megahertz (10 MHz

DECL Documentation
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) signal from a reference oscillator and produce divided and multiplied outputs synchronized to the reference. The DECL module uses two chips, a PLL chip and a microprocessor chip, to convert the rubidium input signal to a logic level and multiply and divide that signal to provide multiple frequency outputs that are related to the reference. The PLL chip conditions the input signal to provide a buffered, logic-level output. This output also drives the microprocessor clock input. The PLL provides a multiplied output, typically 25 MHz, for use as a stable phase-locked output that is derived from the input reference frequency. The microprocessor takes the buffered output of the reference signal and divides it to produce marker signals at various frequencies from 1 MHz to 1 Hertz. The microprocessor and its code are the same as used for the DECUS decade divider module. The schematic shows the components, circuitry and some operational information for the module. For example, the schematic includes a table for PLL jumper options and bottom-side component placement for the DECL PC Board. The Parts List provides additional information about the components used to assemble the module. Photo 1, the module measures approximately 1 1/4 by 7/8 inches (32 by 23 mm). This is the same size as the the DECUS module. Signal connections are provided on two 12-pin single-row pin headers. The header connections are labeled "A" to "X" for easy...

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