Digital Clock

  
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The 7490 counter is a negative edge triggered decade counter that counts from 0 to 9. Pins CLKB & QA must be connected for this counter in order that it would operate in the decade mode. The inputs R0(1, 2) & R9(1, 2) are asynchronous reset pins, one of each must be low for counting, if both the R9(1, 2) inputs were high, then the counter will be res
Digital Clock - schematic

et to 9, while if both the R0(1, 2) inputs were high while one of the R9(1, 2) inputs was low, then the counter will be reset to 0. Since the number indicating the minutes or seconds consists of 2 digits, then 2 counters are used, the one on the right counts from 0 to 9, while the one on the left counts from 0 to 5. For the counter on the right, the bit QD goes from HI (ie: 1) to LO (ie: 0) only in one condition, that is when the count goes from 9 to 0 (ie. from 1001 to 0000 in binary), so, it is used to trigger the counter which is on the left, so whenever the count goes from 9 to 0 at the counter on the right, the counter on the left will be triggered and incremented by 1, till the count becomes 6. For the counter on the left, the outputs QB & QC are connected to the R0(1, 2) inputs, so when the count becomes 6, the counter will be immediately reset to 0. Hence this stage will count from 00 from 59. Since the output QC for the counter on the left goes from HI to LO only when it is reset from 6 to 0 (ie. 0110 to 0000 in binary), so, it is used to trigger the counter in the next stage. The seconds stage is triggered by a 1 Hz astable multivibrator stage, the minutes stage is triggered by the QC output of the seconds stage (which is labelled "out CLK pulse" in the figure), and the hours stage is triggered by the QC output of the minutes stage. Since the maximum hour is 12, then the first digit is either 0 or 1, therefore...



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