FET biasing

Posted on Feb 5, 2014

Unlike BJTs, thermal runaway does not occur with FETs, as already discussed in our blog. However, the wide differences in maximum and minimum transfer characteristics make ID levels unpredictable with simple fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents ID and drain-source voltage VDS, source resistor and potenti

FET biasing
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al divider bias techniques must be used. With few exceptions, MOSFET bias circuits are similar to those used for JFET s. Various FET biasing circuits are discussed below: DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain current ID. For a JFET drain current is limited by the saturation current IDS. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET. Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always negative with respect to source and no current flows through resistor RG and gate terminal that is IG =0. The battery provides a voltage VGS to bias the N-channel JFET, but no resultingcurrent is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any ac signal will develop across RG, the dc voltage drop across RG is equal to IG RG i. e. 0 volt. So voltage drop across resistance Rs provides thebiasing voltage VGg and no external source is requiredfor biasing and this is the reason that it is called self-biasing. Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance. Let the given JFET be replaced by another...

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