Few words about CPLD


Posted on Feb 4, 2014

I forced myself to use and learn about programmable logic chips. As I wrote in my older post, I have very small inventory of the chips and was forced to use Lattice isp2032VE110LT144 chip. I received great help reading article from Seattle Robotics Society web page. Also, at same time I was experimenting with controller-less LCD screen module. So


Few words about CPLD
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I joined both ideas to one project and here is the result. The theory about LCD control was tested using big computer and MS Visual Basic software. CPLD programing software I downloaded from Lattice Semiconductors site. The chip was soldered to self-made testing PCB. I started ispLever Navigator and started my project from nill. I not too smart to wrote all signals is HDL (hardware description language) so I selected mixed type of the project: ABEL + Schematics. So I can describe some modules in ABEL language and connect all modules using graphics editor in schematics editor. I selected ABEL as I had some examples already written in it. In theory I need to feed LCD with clock, vsync and hsync pulses. It is very easy to describe column and row detection logic modules. Here is row detector (eiles. abv) In ABLEL language there are few mandatory fields: MODULE name of the module; declarations- declaration of the variables and wires; equations- the logic formulas itself. In this example we use whole bunch of wires or bus called a[] a8, a9, a10 and etc. up to a15. I collected wires to bus for easy description. In equations section we just test the bus for some value. The column detect is identical (stulpai. abv): The binary counter is a bit more complicated. I use two types of counters in this project- one is 4 bit counter for dividing frequency of master clock (count4. abl): This counter is created using example. I only...




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