How to design 65nm FPGA DDR2 memory


Posted on Feb 6, 2014

This article presents practical techniques for incorporating `correctness by design` in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives. Several possible address/control t


How to design 65nm FPGA DDR2 memory
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opologies for DDR2 shown in Fig 1, while several possible data topologies are illustrated in Fig 2. In order to make use of the FPGA`s on-die digitally controlled impedance (DCI), the memory chip was made the driver and the 65nm FPGA device the receiver on the bi-directional data lines. The top schematic diagram in Fig 1 shows the preferred and recommended use model, while the other figures illustrate variations often attempted in regular design practice. The input switching thresholds of the receiver are shown as horizontal dashed blue lines for reference. The color of the "probe" arrows in Fig 1 and Fig 2 correspond to the colors of the associated traces in Fig 3 and Fig 4, respectively. Mentor Graphics` HyperLynx software was used to generate eye diagrams with the following parameter settings:




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