I2C Bus I2C Interface description

  
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The I2C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. Both the SCL and SDA lines are pulled high via an Rp resistor. Resistor Rs is optional, and used for ESD protection for `Hot-Swap` devices. No other lines are specified. Any device may be a Transmitter or Receiver, and a Master or Slave. Data and clock are sent
I2C Bus I2C Interface description - schematic

from the Master ~ valid while the clock line is high. The link may have multiple Masters and Slaves on the bus, but only one Master may be active at any one time. I2C Slaves may receive or transmit data to the master. I2C, due to its two-wire nature (one clock, one data) can only communicate half-duplex. The maximum bus capacitance is 400pF, which sets the maximum number of devices on the I2C bus and the maximum line length. The interface uses 8 bit long bytes, MSB [Most Significant Bit] first, with each device having a unique address. Data on the SDA data line only changes when the clock line [SCL] is low. However if SDA drops while SCL is high a start of frame is indicated. Also if SDA rises while SCL is high than a stop condition is indicated. The Start condition indicates a start of frame and the Stop condition indicates an end of frame. Each transfer on the I2C is 9 bits long, eight data bits followed by a `1` bit. The listener acknowledges the receipt of the byte in one of two ways; the listener may over write the `1` bit with a `0` bit indicating ready for more data. or leaving the trailing `1` indicating not ready for data. The Master [talker] always generates the clock and the message. An I2C message begins with a Start bit, followed by a 7 bit Slave address and then a direction bit [`1` for Read, `0` for Write]. Once the slave address is sent, the slave is required to respond, otherwise the master will send a Stop...



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