Inverter size strength

The different strengths between the PMOS and NMOS transistors can be observed through a simple test of ramping up the input voltage an observing the point at which the output voltage will switch from 5V to 0V. To perform this test, click on the cell named Inverter_var_test  and open the schematic  view (refer to Screenshot 5). You will notice
Inverter size strength - schematic

that the circuit now consists of the inverter with some voltage sources, one providing power to the circuit (V0), one providing the input signal (v1). Now click on the Tools  menu up in the top left hand corner. Then select Analog Environment  and a new window will open up (refer to Screenshot 6). Now you will need to run the simulation. This is done vie either clicking on Simulation  and selecting Netlist and Run  or by clicking directly on the Netlist and Run  button (refer to Screenshot 9). The simulation will open up an Output Log  (refer to screenshot 10) detailing the simulation while the simulation runs, and once the simulation finishes, an Output Waveform  window will appear with the input and output waveforms (refer to screenshot 11). From this window (refer to screenshot 11) you will notice that as the input voltage to the inverter circuit is increased the output voltage will switch from 5V to 0V, representing a switch from a 1 value to a 0 value. You will notice however, that the point that the output switches is not at the middle of the input range. As mentioned before, this is due to the fact the NMOS switching on more strongly than the PMOS switches off, represented as the NMOS resistance being smaller than the PMOS resistance. The exact switching value is provided by the In->Out Cross (V)  output to be 2. 164V.

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