LC compliant boost converter circuit diagram

  
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The main ΣΔloop, which again operates in steady state, is fully controlled by summing comparator Q2, which amplifies the ripples of the sensed inductor current and output voltage by gains KI and KV, respectively, to generate an internal variable s. This variable s , is regulated to zero by the feedback control action of Q2, as in conventional sliding-mode control. In steady state, auxiliary switch MPP3 is always open and the bypass ΣΔ block containing comparator Q1 is inactive.
LC compliant boost converter circuit diagram - schematic

The main loop gives wide LC filter compliance and low output voltage ripple since it adheres to the teachings of sliding-mode ΣΔ control. However, the transient response is slow because it is defined to meet the requirements of the worst-case LC specifications. This slow response is corrected using the fast bypass ΣΔ loop during transient events. The bypass ΣΔ loop, operating during transient events only, is controlled by comparator Q1, which senses and controls the output voltage through the duty-cycle of switch MPP3. During bypass conditions, when the output voltage drops below the predefined window limit set by Q1, the bypass loop regulates the output voltage (VS) to VREF, irrespective of the inductor current, forcing the average inductor current to increase, since its dIL/dt is now mostly unidirectional. This current consequently increases beyond its minimum average value ILMIN (inductor current IL equals ILMIN during steady-state conditions) and only drops back down when the output voltage again reaches its prescribed window limits, at which point MPP3 is disabled. Comparator Q2 only regulates the sensed inductor current to its reference value, which is the DC value of the sensed current. This current loop is therefore independent and self-sustaining and the inductor current, as it is, is regulated and constant. A higher-than-minimum inductor current leads to increased power losses and a higher output voltage ripple,...



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