Posted on Feb 5, 2014

This circuit is based on the 7240 CMOS programmable timer chip (IC3), which has an accuracy of 0. 5 percent. It contains a time-base generator, the frequency of which is decided by a resistor and a capacitor. The basic time period is RC seconds; so, given that the maximum value of R is 10 M © and the maximum value of C is 1000 F, the maximum time

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period is 10, 000 seconds, (2. 8 hours) IC3 also has an eight-stage binary divider chain. The total period available is 27 times the above, which is just over 14 days. In this figure, S1 is an optional power switch. S2 is the switch which is closed to initiate timing. Closing S2 generates a brief low pulse that goes to pin 11 of the timer IC3 and starts the timing. The output of the timer is normally high, but it goes low for the whole of the timing interval. The length of the interval is selected by a rotary switch S3. Pins 1 to 8 of IC3 are the outputs from the eight-stage divider chain. When the counter is reset, they all go high; while timing, they go through an inverted binary sequence. R5 connects the output to the RESET terminal (pin 10), so the counter is reset at the end of the interval. The first stage of the logic consists of two NOR gates and a NAND gate wired as an inverter (part of IC1, 4011). These gates detect the two alarm states. A high output on either pin 8 or pin 9 causes a low output from gate IC2c (pin 10). This makes the RESET input of IC4 low. IC4 is a 14-stage counter with its own oscillator, which begins to oscillate when the RESET is made low. The oscillator has a period of about 25 kHz, which is divided down to produce 1. 6 kHz at pin 7 (high-pitched note), 200 Hz at pin 6 (low-pitched note), 6 Hz at pin 1 (fast bleeping), and 1. 5 Hz at pin 3 (slow beeping). The remainder of the logic consists...

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