Mini LOGGER V1.0 Block Diagram


Posted on Feb 5, 2014

A simplified block diagram of the MiniLOGGER is shown in Figure 1. The CMOS analog multiplexer, 4051 provides the output for 8-channel single-end input to an analog-to-digital converter chip, CA3162. The CA3162 is connected in free running mode. The digital output is 4-bit BCD started with MSD, NSD, and LSD. The pulse period of MSD is 2ms. The 89C


Mini LOGGER V1.0 Block Diagram
Click here to download the full size of the above Circuit.

2051 runs solar3. hex, the firmware that controls 8-channel reading and receives external pulse. When the chip was triggered by INT0 signal, it will send the digital value in ASCII format through TxD pin; The 89C55 reads such record with time stamped read from DS1202 and saved into SRAM. Now it saves also DATE/TIME and provides comma for each channel separation. There`s also a supervisory and power supply chip, MAX691 for battery backup to SRAM and RTC, MAX232 for RS232 converter, and ICL7660 negative voltage converter.




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