STEREO TV DECODER

  
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A block diagram of the stereo-TV decoder is shown in A. It shows the overall relationships be-tween the separate sections of the circuit; B through E show the details of each subsection. The de-coder section centers around IC1, a standard 4. 5-MHz audio demodulator. The output of IC1 is routed to 51, which allows you to choose between the internall
STEREO TV DECODER - schematic

y demodulated signal and an exter-nally demodulated one. Buffer amplifier IC2-a then provides a low-impedance source to drive IC3, an LM1800 stereo demodulator. When IC3 is locked on a stereo signal, the outputs presented at pins 4 and 5 are discrete left- and right-channel signals, respectively. In order to provide noise reduction to the L-R signal, you must recombine the discrete outputs into sum and difference signals. Op amp IC4-a is used to regenerate the L-R signal. It is wired as a difference amplifier, wherein the inputs are summed together (+L -, R). Capacitor C18 bridges the left- and right-channel outputs of the demodulator. Although it decreases high-frequency separation slightly, it also reduces high-frequency distortion. The L + R signal is taken from the LM1800 at pin 2, where it appears at the output of an internal buffer amplifier. The rawL -R signal is applied to IC4-b, a 12-kHz lowpass filter. The L + R signal is also fed through a 12-kHz low pass filter in order to keep the phase shift undergone by both signals equal. Next, the L - R signal is fed to Q2. It allows you to add a level control to the L - R signal path; it provides a low source impedance for driving the following circuits, and it inverts the signal 180 °. In-version is necessary to compensate for the 180 °inversion in the compander. Next comes the expander stage. At the collector of Q2 is a 75- s de-emphasis network (R27 and C29)...




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