Sequencer circuit

Posted on Feb 6, 2014

First, the 4017`s aren`t initialized to a known state since the reset pins aren`t briefly forced high when the circuit powers on. The chips might usually power up in the normal reset condition, but that isn`t probably guaranteed by the IC manufacturer. This is probably only a minor concern. Second, on the IC2 4017, outputs Q2 through Q9 are shorted together and tied to the reset pin.

Sequencer circuit
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This is a major design flaw. This appears to be an attempt to modify the design of the lower schematic you provide. In that design, there are only 20 outputs used, and when IC2 toggles Q2 high, that high will reset IC2 back to Q0 being high. In your upper schematic, if you are really using all 10 banks of outputs on IC2, none of the outputs need to feed back to the reset pin. Regardless, only certain types of logic can tolerate outputs being shorted together, and the 4017 isn`t one of them. Third, tying an output pin back to the asynchronous (instantaneous, not on a clock edge) reset pin creates what is called a race condition. The width of the reset pulse will only be as long as the propogation delay from the reset pin to the output pin driving it. While this might work, there are a lot of circuit designers who wouldn`t do that. This is also probably only a minor concern. I agree with Cat that a 4017 can`t drive the positive side of a relay. Doing so might work for some reason (as the relay clicks in Janneman1`s video seems to prove), but unless you are using extremely sensitive relays that take little current to energize them, you are violating the output drive spec of the 4017. I don`t know - maybe it works for very short relay pulses, or maybe the chip will put up with this for a while, but this is another major concern. Cat, the 555 schematic you pasted in isn`t the right one. That schematic is the monostable mode...

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