Serial PCI Express Bus


Posted on Feb 5, 2014

The PCI Express [PCIe] bus defines the Electrical, topology and protocol for the physical layer of a point to point serial interface over copper wire or optical fiber. In addition to the Physical Layer, the PCI Express specification also covers the Transaction Layer and Data Link Layer. The Physical Layer resides with Layer 1, and the Data Link La


Serial PCI Express Bus
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yer resides with Layer 2 of the OSI protocol model. PCI Express is the new serial bus addition to the PCI series of specifications. How ever the electrical and mechanical interface for PCI Express is not compatible with the PCI bus interface. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2. 5Gb/s in each direction [one transmit, and one receive pair]. A PCI Express link is comprised of these two unidirectional differential pairs each operating at 2. 5Gbps to achieve a basic over all throughput of 5Gbps [before accounting for over-head]. PCI Express uses 8B/10B encoding [each 8 bit byte is translated into a 10 bit character in order to equalize the numbers of 1`s and 0`s sent, and the encoded signal contains an embedded clock]. PCI Express supports 1x [2. 5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs]; 2. 5Gigabits/second per Lane per Direction. The 8B/10B changes the data transfer numbers to 250MBps per lane, raw data [B= Bytes, b=Bits]. The reduction in throughput is accounted for under the protocol section. Revision 3. 0 (Gen 3) due out in 2010 increases the speed to 8GT/s and changes the encoding to 128b/130b to reduce the over head. The new bandwidth will increase from 4Gb/s (Gen 2) to 7. 99Gb/s both from over head reduction and bit time reductions. Note; Giga-Transfers per Second (GT/s) The basic LVDS interface is a single differential link in either one or...




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