Simple Combination Lock

  
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This simple combination lock accommodates codes from 1-9 digits long, with the only restriction being that the same digit cannot be used twice. The circuit shows strapping for a 4-digit code, in this case `2057`. Any unused switches are strapped to ground. When power is applied, the 330nF capacitor connected to pin 1 of inverter IC1a is discharged
Simple Combination Lock - schematic

, holding it at a logic low level. The high output is inverted by a second gate (IC1b), with the result being a logic low on pin 4. This pulls Q1`s emitter low via D1, causing the transistor to conduct. The falling voltage on the collector then pulls the input of IC1c low, which in turn resets counter IC2. On reset, output O0 (pin 3) of IC2 goes high, charging the 330nF capacitor via D2 and the 33k © resistor. If switch S2 is now pressed, Q2`s emitter will be pulled high and so Q2 conducts, applying a rising positive voltage to one end of the 1M © resistor. This resistor and the 33nF capacitor act as a switch "debounce" circuit, delaying the pulse through IC1e by about 33ms. After the delay, the output of IC1e goes low. However, counter IC2 does not increment at this stage, since it needs a positive-going edge at the clock input (pin 14). When the switch is released, Q2 turns off, IC1e`s output goes high after the debounce period and the counter advances to the next state (ie. O0 goes low and O1 goes high). When output O0 (pin 3) goes low, the 330nF capacitor starts discharging through the 33k © and 10M © resistors. This allows about 3s for the operator to press the next button. If no button is pressed within this period, IC1b`s output goes low, which pulls Q1`s emitter low and resets the counter via IC1c. Hence the code entry must be restarted. When the second digit of the code is entered (0 in this example), Q2`s emitter...



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