Synchronous Counters

The material is presented in a manner suitable for a teaching tool. It seeks to enlighten and to spark off interest in the design of counters. As R. S. S Obermann remarks `. design of counters has, in my experience, always been an excellent proving ground for anyone who has mastered Boolean algebra. Have fun reading ! A synchronous binary counter
Synchronous Counters - schematic

counts from 0 to 2N-1, where N is the number of bits/flip-flops in the counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order position is complemented/toggled with every clock pulse and a flip-flop in any other position is complemented on the next clock pulse provided all the bits in the lower-order positions are equal to 1. Take for example A4 A3 A2 A1 = 0011. On the next count, A4 A3 A2 A1 = 0100. A1, the lowest-order bit, is always complemented. A2 is complemented because all the lower-order positions (A1 only in this case) are 1`s. A3 is also complemented because all the lower-order positions, A2 and A1 are 1`s. But A4 is not complemented the lower-order positions, A3 A2 A1 = 011, do not give an all 1 condition. To implment a synchronous counter, we need a flip-flop for every bit and an AND gate for every bit except the first and the last bit. The diagram below shows the implementation of a 4-bit synchronous up-counter. From the diagram above, we can see that although the counter is synchronous and is supposed to change simultaneously, we have a propagation delay through the AND gates which add up to give an overall propagation delay which is proportional to the number of bits of the counter. To overcome this problem, we can feed the outputs from the flip-flops directly to a many-input AND gate as follows : This method does overcomes the problem of additive propagation delay but...

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