Analog-to-digital converters are classified into one-step architectures, such as: flash, folding and interpolative topologies, and multi-step architectures, such as: Successive approximation and pipeline topologies. The flash architecture is potentially the fastest analog-to-digital converter, because of the parallelism it employs. However, this p

arallelism puts a practical limit on the resolution of the flash analog-to-digital converter. For an n-bit analog-to-digital converter, the flash architecture employs (2 n 1) comparators and decoding logic. A resistive ladder consisting of 2 n equal resistors divides the reference voltage into 2 n equally spaced voltages as shown in Figure 7. 15 is logic 0. The decoding logic transfers the thermometer code which has (2 n 1) bits into a binary signal which has n bits. Table 7. 1 shows the mapping between the thermometer code and the binary coded signal when n=3.

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