dual slope sampling SE

Posted on Feb 5, 2014

If you had time to experiment with the ALF type SE circuit you may have discovered some of its shortcomings with regard to a Power Smart Head adaptation. The problem is that HCMOS gates are power hungry when used as SE voltage comparators when the analog input voltage is near the CMOS switching threshold. If an HCMOS gate is used without sampling, the

dual slope sampling SE
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chip supply current can be as high as 70mA with the comparator input voltage near the trigger threshold ( Vcc / 2). Sampling the analog input voltage, which represents the level of Vcc, with narrow pulses can reduce power supply current by the on / off ratio of the sampling pulse width. With the ALF circuit the worst case average current during a sampling period with a comparator input voltage near the threshold is reduced to less than 100uA although the peak currents will still be in the 50ma range. Once the ALF circuit is triggered, the rest of the circuit which the SE controls is enabled and becomes active. During this active period, the main storage capacitor is quickly discharged through the load with a duration much shorter than the charging time. This is an important consideration since the same high chip supply current s caused by analog voltages at the comparator input during charging also occur during the discharge period. For circuits like the Power Smart Head, that have a low power standby mode when locked on to balanced light, the discharge time can take much longer. In the standby mode, the total circuit supply current may be less than 1mA which would conserve the charge on the main capacitor to many tens of minutes if it were not for the inefficient method used to compare the reset voltage level. During the discharge, the analog comparator input voltage is not sampled and the chip current will rapidly...

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