ethernet Poor eye diagram where to start looking


Posted on Feb 6, 2014

This is the eye diagram for the transmit pair. The receive pair is very similar. It`s a LAN8700 PHY, and I`ve got the MII interface effectively disabled, so the PHY is transmitting IDLE code sequences. It`s forced into 100Mbit/FDX as per the datasheet. 100Mbit/HDX is identical. Correction: The design is using the LAN8700`s internal 1. 8V supply to


ethernet Poor eye diagram where to start looking
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power its VDD_CORE net; I must have been confusing the 1. 8V logic supply with the VDD_CORE supply in my earlier description. It seems to me that power supply noise is not such a high likelihood, since the high, zero and low levels are actually pretty decent. That is, the eye isn`t "squished. " The fact that the violations all look like very good transitions, just "skewed" in time makes me think the problem lies in the crystal or supply for the crystal driver/PLL in the PHY. If I let the eye diagram run (about 15min) the violations in the mask "fill in" such that the white violations you see in the picture become white chevron (>) shapes in the right-hand sides of the blue masks. This would tell me that the timing errors are more or less randomly distributed rather than some kind of discrete noise yanking the timing off an exact amount. The crystal that the PHY is using has a 30ppm spec which is well within the 100ppm 802. 3 spec, and even within the 50ppm recommended spec that the PHY specifies. I`m using loading capacitors which match what the crystal is looking for, and is pretty close to what the LAN8700 specifies as its nominal capacitance. Before I disabled the MII interface I would see framing errors (as reported my Linux`s ifconfig program). There are no errors if I force the link to 10Mbit. One of the very odd things I have noticed is that if I set the scope up to trigger on the RX_ER (receive error) signal from...




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