op amp Why do some of my IE converter circuits have a large offset voltage


Posted on Feb 4, 2014

The inverting input is held low through a 10K resistor when the circuit is powered on but not being used. Whenever a measurement is being made (including calibration measurements where IN is floating), that resistor is disconnected. The circuit is used to measure currents in the nanoamp range. A few mV on the output is significant. Constant offsets are not


op amp Why do some of my IE converter circuits have a large offset voltage
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really a problem, as they can easily be calibrated out by measuring the output with an open input and subtracting that from subsequent measurements. SW1A and SW1B are different poles of the same CMOS switch (ADG1236). They are switched together to select the feedback resistor, which determines the gain of the converter. The maximum leakage current is 1 nA on source and drain pins, on or off. The switch not shown (for holding the inverting input low through a 10K resistor) has similar performance. Typical leakage currents are very small (< 0. 1nA). The problem I am having is that in some batches of boards, some (or all) of these circuits have large offsets which decay slowly when powered on. However, most boards are perfectly stable at all times, with small offsets. When the afflicted boards are powered on, the offset will slowly (after hours of days) stabilize to ~5 mV. After power is removed, the offset accumulates again, so when powering it on after a couple days of being off, it`s high again. Each board has a bunch of these circuits on it. In the first batch of 5 boards, all of them were affected. In the next batch, none were affected. In the most recent batch, each board has one affected circuits, and it isn`t always the same one. At the worst case, the maximum leakage currents of all the analog switches would be 1. 2nA, resulting in a 12 mV offset at the highest gain setting, so I don`t think that can account for all...




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