power supply NMOS FET selection for reverse polarity protection


Posted on Feb 6, 2014

A reverse polarity protection circuit, similar to that in Figure 2 of SLVA139: Reverse Current/Battery Protection Circuits. Here is my circuit: My case is slightly more complex due to the possible input voltage ranging from 5-40V. Most MOSFETs seem to have a maximum gate-source voltage VGS of 20V, so I need the Zener clamp on thegate (or a very large/expensive FET).


power supply NMOS FET selection for reverse polarity protection
Click here to download the full size of the above Circuit.

The maximum input current will be about 6A. What I`m wondering is, what FET characteristics actually matter in this configuration I know that I definitely want a drain-source breakdown voltage BVDSS high enough to handle the full input voltage in the reverse polarity condition. I`m also pretty sure I want to minimize RDS(on) as to not introduce any impedance in the ground circuit. Fairchild AN-9010: MOSFET Basics has this to say about operation in the Ohmic region: "If the drain-to-source voltage is zero, the drain current also becomes zero regardless of gate to-source voltage. This region is at the left side of the VGS VGS(th)= VDS boundary line (VGS VGS(th) > VDS > 0). Even if the drain current is very large, in this region the power dissipation is maintained by minimizing VDS(on). " Does this configuration fall under the VDS = 0 classification That seems like a somewhat dangerous assumption to make in a noisy environment (this will be operating in the vicinity of various types of motors), as any voltage offsets between input supply ground and local ground could cause current to flow. Even with that possibility, I`m not sure I need to spec for my maximum load current on the drain current ID. It would then follow that I don`t need to dissipate very much power either. I suppose I could mitigate the problem by Zener clamping VGS closer to VGS(th) to reduce drain current/voltage




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