single cycle datapath write to register and memory at same time

Is it possible to alter a single-cycle datapath so that an add instruction not only writes to a register, but also writes to a specified memory address The only way I can think to do this is to split the value as shown bellow. I don`t think this is possible though. One of the basic principles of RISC architecture is for each instruction to only have one output result. This makes tricks like piplelining and

super-scalar execution much easier to manage. CISC architectures like the PDP-11 and the x86 had instructions with multiple output results, and this made them much harder to design to run fast.

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