telephone ring generator circuit

Posted on Feb 4, 2014

This is a switch selectable dual output `re-hashed` version of my previous (2007) design, and uses a field programmed EPROM for generating both versions of the ringing sequence. AC mains is stepped down to about 10 v AC and fed to the familiar bridge rectifier, filter capacitor and 3 terminal voltage regulator. However a series diode is inserted b

telephone ring generator circuit
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etween the + terminal of the bridge rectifier and the filter capacitor. Therefore at the anode end of this diode will be a pulsating 100Hz unidirectional sinusoid which is used as an accurate "clock" (Cathode end being filtered DC voltage) This positive going sinusoid is fed to a 4093 Schmitt trigger, its action produces a fast rise (and fall) square wave output necessary to clock following logic IC`s. A clamping diode b/w the Schmitt input (pin 2) and the Vcc rail precludes the input from rising greater than one diode drop above Vcc, excess voltage being dropped across 1K resistor. It was found by experiment that a 22K "bleed" resistor was needed at the gate input to prevent "lock-up" due to some sort of "charge storage" effect. This cleaned-up 100Hz "clock" signal is now fed to a 4013 D type flip-flop which divides the signal by 2 and also gives a 50 Hz equi` mark/space signal. This then feeds the 7490 where another divide by 2 gives; 25Hz (for ringing frequency) and further divide by 5 give 5Hz or a 200mS interval suitable for producing the correct ring cadence. The sequential outputs of the 4040 are connected to the address lines of a 2716 eprom which has been field programmed to provide a serial output bit-stream of 200mS interval used as a gating signal to enable on and off the 25Hz ringing signal. For each 200mS clock pulse the output of the eprom moves to the next sequential address. The first 64 locations contain...

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