FPGA makes simple FIFO


Posted on Apr 15, 2012

The circuit in Figure 1 is an FPGA-based, synchronous FIFO that uses the same clock for read and write operations. The circuit can generate FIFO-occupancy flags with a minimum of logic. The boxed area in Figure 1 shows a more conventional occupancy meter. The circuit is implemented in a demultiplexer that writes data in the FIFO when the data arrives and reads data according to FIFO occupancy. The circuit uses a Xilinx Spartan (XC4000 equivalent) FPGA. The method uses three main blocks: a 16-bit dual-port RAM macro, read- and write-address counters, and the flag processor.



In this design, the FIFO is 4 bits deep but can be as great as 16 bits deep using the RAM16X1D macro. Read and write counters can take the form of any cyclic counter, a conventional binary counter, a Gray-code counter, or a linear-feedback shift register.




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