Memory Circuits

The circuit shown below uses three PI5C16861 bus switches. IC1 is used to perform level translation on all control and addressing lines while IC2 and IC3 are used to translate 36 bits of data. All three switches are always enabled because they are used strictly as translators. Notice that if live insertion is required, the bus switch can double as bus isolation. In such a situation, enable pins should be held high with a pullup resistor during insertion...

This technology allows you to use a section of flash memory as if it were EEPROM. Because this µC is a true-flash device, the maximum number of erase/write cycles is typically 100,000 cycles. The flow chart in Figure 1 and the C code in Listing 1 show the adaptation of a textbook LFSR (linear-finite shift register) to the COP8 flash µC...

The circuit of Figure 1 provides the termination voltage for both 1.8 and 2.5V memory systems and delivers output current as high as 6A. IC1 includes a step-down controller and two linear-regulator controllers and operates with input voltages of 4.5 to 28V...

The circuit in Fig 1 increases the memory of Analog Devices` 2101 family of fixed-point DSP µPs. The simple scheme uses only three external static-memory devices and no glue logic. With the additional memory, the DSP µP will have 16k words of program memory and 15k words of data memory. (The memory totals include 2k words of internal program memory and 1k word of internal data memory.)..

A pc board bearing the 16-bit ISA data-bus interface in Fig 1 can adapt automatically to either 8- or 16-bit motherboard slots. The interface comprises three bidirectional octal buffers and glue logic. The glue logic controls transfer direction and output enables...

The circuit converts a 32k½§16 SuperSync FIFO design to bidirectional (half-duplex) using QuickSwitch QS3390 16-to-8 multiplexer/demultiplexer ICs. This implementation has the following advantages over the traditional tristate-multiplex/demultiplex approach:..