Dual 8051S Execute In Lock-Step

This hardware-software combination deletes clocks from the slave until both /iPs synchronize. The firmware
Dual 8051S Execute In Lock-Step - schematic

loop causes each to generate a WR signal once per loop. The circuit exclusive-ORs the two WR signals to produce a miss-compare pulse. The miss-compare pulse latches into the two JK flip-flops via outputs LOCKSTP1 and LOCKSTP2. A high on these signals indicates that the /tPs are in lock-step, causing both juPs" programs" execution to exit the firmware loop. If you use discrete components, you"ll probably want to use the Q output of the JK flip-flop and delete the circuit"s inverters. The listing uses the /iPs" ports 1 and 3. You cannot use a memory-mapped location for the lock-step-detect clear (K input) because this scheme would generate additional WR signals. You could apply this idea to other, perhaps using their RD signals. This way, generating an RD signal to activate the lock-step-detect clear would not affect the synchronization inputs.

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