ESD Testing for RS232 Interface Circuits


Posted on Mar 10, 2013

The machine model, commonly used for ESD testing in Japan, is a more severe ESD test. This model simulates metallic contact between the device under test and a charged body. The source capacitor is 200pF with no limiting resistor. The higher source capacitance and the absence of a limiting resistor causes the device under test to be subjected to more voltage, energy, and current than human body model testing. Therefore failures occur at lower test voltages with machine model than with human body model testing. LTC’s RS232 transceivers can withstand ±3.5kV when tested with the machine model. The IEC-801 test method fi ts between the human body and machine methods in severity. The source capacitor is 150pF with a 330Ω limiting resistor. LTC’s RS232 transceivers pass test voltages of ±7.5kV with the IEC-801 method.


ESD Testing for RS232 Interface Circuits
Click here to download the full size of the above Circuit.

ESD Transients During Powered Operation The test methods discussed so far involve testing for permanent damage to the integrated circuit from ESD transients. In today’s portable electronics, interconnection of cables to the communications ports may occur while the equipment is operating. This makes it imperative that the circuit can tolerate the ESD transient with minimal disruption of system operation. LTC’s RS232 interface circuits can withstand 10kV ESD transients while operating, shut down, or powered down. Disruption of data transfer is unavoidable during the ESD transient event, but data transmission may resume upon the completion of the event. Figure 2 is a scope photograph of the data transmission interruption and recovery seen when a –10kV ESD transient strikes a communications line. The test circuit of Figure 3 was used to record this event. The ESD strike is applied to the driver output of an LT1180A and the receiver input of an LT1331. The ESD transient is of too short a duration to be recorded on the photograph, but the effects of the transient can be seen by the corruption of data after the strike. The circuits require about 20μs to recover from the event, after which data transmission continues normally





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