Hot Swapping the PCI Bus

Posted on Jan 8, 2013

The circuitry for a hot swappable PCI slot on a motherboard or backplane is shown in Figure 1. The power supplies for each PCI slot are controlled by an LTC1421 and four external FETs, and the data bus is buffered by several QS3384 QuickSwitches or equivalent. A PCI power control ASIC, FPGA, microprocessor or the like, controls all of the slots within the system. The 12V, 5V, 3.3V and – 12V supplies are controlled by placing external N-channel pass transistors, Q1 to Q4, in the power path. By increasing the voltage on the gate of the pass transistors at a controlled rate, the transient surge current (I = C • dV/dt) drawn from the PCI supplies can be limited to a safe value. The ramp rate for the positive supplies is set by dV/dt = 20μA/C2. The –12V supply ramp rate is set by R7 and C3, while resistor R5 and transistor Q5 help turn off transistor Q2 quickly. Resistors R9, R11 and R12 prevent potential high frequency FET oscillations. Resistors R13 and R14 pull up PWRGD and FAULT to the proper logic level.

Hot Swapping the PCI Bus
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Sense resistors R1, R2 and R3 provide current fault protection. When the voltage across R1 and R2 is greater than 50mV for more than 10μs, the LTC1421 circuit breaker is tripped. All of the FETs are immediately turned off and the FAULT pin is pulled low. The circuit breaker is reset by cycling the POR pin. The current fault protection for the 3.3V supply is provided by resistive divider R6 and R8 and the uncommitted comparator in the LTC1421. Because the current levels on the –12V supply are so low, overcurrent protection is not necessary. The QuickSwitch bus switch contains a low resistance N-channel placed in series with the data bus. The switch is turned off when the board is inserted and then enabled after the power is stable. The switch inputs and outputs do not have a parasitic diode back to VCC and have very low capacitance. System Timing The system timing is shown in Figure 2. The PCI power controller senses when a board has been inserted into the PCI via the power-select bits. Alternatively, the user can inform the controller that a board has been inserted via a front panel or keyboard. The PCI controller holds the RST# pin low and disables the QuickSwitch bus switches, then turns on the LTC1421 via the POR pin. The power supplies turn on at a controlled rate and when the 12V supply is within 10% of its fi nal value, the PWRGD signal pulls high. The PCI power controller waits one reset time-out period...

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