The circuit uses one-half of a dual D flip-flop as an inverter. When the input decreases, the flip-flop resets, and its Q output increases. When the input increases, the reset line is released and Q gets clocked low. The rc delay between applying the input signal to the flip-flop`s reset input and its clock input enables clocking the flip-flop on the input`s positive edge. A 74HC74 dual D flip-flop, for example, requires a minimum recovery time of 5 ns after releasing the reset input before strobing its clock input.
Spare-flip-flop-inverter - schematic

Therefore, speccing rc at greater than 7.5 ns provides adequate margin. The slight slowing of the clock edge presents no problem, because the clock input"s maximum allowable rise time is a much longer 500 ns. To prevent skewing ofthe output"s symmetry, limit the maximum input frequency to less than 10 MHz.

Leave Comment

characters left:

New Circuits