Z-80 Bus Monitor/Debugger

  
Getting microprocessor designs to work is notoriously difficult when both the software and hardware are new. The
Z-80 Bus Monitor/Debugger - schematic

usual approach is to run test routines that address memory and I/O, but do not rely on their correct functioning. However, miswiring in any part of the circuit usually leads to a misleading jumble of signals that might require a logic analyzer to interpret. This simple circuit will trace the program execution and help point to the problems. Although the circuit shows connections for a Z-80, the circuit can very easily be adapted for any 8-bit microprocessor or with additional circuitry for CPUs of any bus width. The circuit consists of a 5-byte hexadecimal display and comparator, which are wired to a 40-pin IC test clip. The test clip sits over the microprocessor (in this case a Z-80), where it gets power and all the required signals. The address bus and control lines are fed to the comparator, where (by means of switches) a trigger condition can be set. Following the trigger, the next 5 occurrences of either RD or WR will latch the contents of the data bus into the 5 hex displays, each in turn. For example, select address 0000 Ml Rd and reset the CPU. The displays will show the very first instruction fetch, followed by its data and any consequent action. Even details, such as stack writes and subroutine addresses, are included. To trace longer portions of a program the address switches can be incremented to follow the execution path.




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