Adc Poller Circuit

  
Because the CS5501 16-bit-delta-sigma analog-to-digital converter lacks a start convert command, it converts continuously, outputting conversion words to its output register every 1024 cycles of its master clock. However, by incorporating a standard dual J-K flip-flop into the circuit, the ADC can be configured to output a single-conversion word only when it is polled.The CS5501 converter can be operated in its asynchronous communication mode (UART) to transmit one 16-bit conversion word when it is polled over an RS-232 serial line (see figure). A null character (all zeros) is transmitted to the circuit and sets the flip-flop PF2. The CS5501 can then output a single-conversion word, which is transmitted over the RS-232 line as two bytes with start and stop bits.
Adc Poller Circuit - schematic

The baud rate can be chosen by selecting the appropriate clock divider rate on the 74HC4040 counter/divider as the serial port clock (SLCK) for the ADC. This type of polled-mode operation is also useful when the ADC`s output register is configured to operate in the synchronous-serial clock (SSC) mode. In this case, the converter will load one output word into a 16-bit serial-to-parallel register (two 74HC595 8-bit registers) when polled to do so (see figure).




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