This receiver consists of an input network amplifier IC7 FSK PLL detector ICG, and output am
plifier/ interface Q2, Q3, IC3A and IC3B, a 1488 Quad RS232 line driver of the carrier-current signal. Tuned amplifier IC7 amplifies this signal and drives PLL detector IC8. The values shown in the circuit are suitable for operation in the 100-kHz range. Recovered data at pins 5, 6, 7 is fed to the output amplifier/interface circuit (Fig. 6). This circuit is also used with the carrier-current data transmitter to form a pair.