6 digits dynamic display circuit

  
Shows - typical of six dynamic display circuit. In the figure, the PA 8255 end date display output code. PB port output bit election code. Let the display buffer is DISBUF, then complete
6 digits dynamic display circuit - schematic

the number (hexadecimal) to be taken after 8255 to initialize a display, using software decoding method determined to be 7-segment display control corresponding to the number displayed by the team and then port the code j output, and after 74LS07 drive to enlarge the display of data on each bus. In the end what a digital display, depending on the location of the election code. Only bit line select signal corresponding PB port after the drive goes low, the corresponding bit will not be emitting display. If you are displayed in order from left to right, each successive digital display period of time (such as Ims), after the last digit is displayed, then repeat the process, so that the human eye can see is the 6-digit "simultaneously" display. Wherein 74LS07 to six drives, which raise the LED drive current for certain. 8255: As a 74LS07 only six drives, so the 7-segment requires two 74LS07 driving after PB port 75452 via buffer / inverting drive, 'as a bit selection signal. A 75452 includes two internal buffers / drivers, each buffer red / driver has two inputs. Drive six LED display requires 3 75452.




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