Digital-logic-probe

  
The probe relies on the power supply of the CUT (circuit-under-test). The input to the probe, at probe tip, is fed along two paths. One path flows to the clock inputs of U2a and U2b. The other path feeds both the inverting input of Ulc, which is set up as an inverting-mode integrator, and the noninverting input of Ulb, which is configured as a noninverting unity-gain amplifier, in a logic-low state. That low, below the reference set at pin 10, causes Ulb`s output at pin 7 to become high.
Digital-logic-probe - schematic

With Ubl outputting low and Ulc outputting high, LEDl is forward-biased, and lights. LED2, reverse-biased, remains dark. Suppose that the logic level on the same pin becomes high. That high is applied to pin 5 of Ulb, causing its output to be high. LED2 is now forward-biased and lights, while LEDl is reverse-biased and becomes dark. Assume that a clock frequency is sensed at the probe input; LEDl and LED2 alternately light, and depending on the frequency of the signal, can appear constantly lit. That frequency, which is also applied to the clock input of both flip-flops, causes the Q outputs of U2a and U2b to simultaneously alternate between high and low. Each time that the Q outputs of the two flip-flops decrease, the output of Uld increases, lighting LED3, indicating that a pulse stream has been detected.




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