Fast Binary Adding Circuits

  
Some circuits that add binary numbers have problems with time delay caused by carry propagation. This has been
Fast Binary Adding Circuits - schematic

partially solved by the carry look-ahead adder. However, because of the complexity of this scheme, the carry look-ahead logic usually covers no more than 4 bits, and a ripple carry is implemented between the carry look-ahead blocks. The Daniels Adder avoids these problems by presenting a scheme where carry bits are not used at all in the process of binary addition. It is based on recognition patterns, which exist with the binary addition truth table. The addition is described by the following two sets of equations: with the boundary condition that q_i = 0, where in, j„, and k)t are the bit of binary weight 2n (nth bit) of the addend, summand, and sum respectively, qn is an intermediate variable and qn is the inverse oiqn. The value of the sum is (depending upon in and ;„) either the same as or the inverse of (depending upon ift- and aO, al, or the inverse of the («-l)th bit of the sum. Figure 45-1 (a) shows the logic diagram of the ripple through implementation of the adder. Because each stage calculates whether its value of the intermediate variable q„ is the same as the previous stage"s value (g„_i) in parallel, it is possible to devise simple "same as" logic that does not have the complexity drawback of carry look-ahead logic and can be carried over any number of bits (Fig. 45-1 (b)). A 32-bit adder built in this way will result in 11-gate delays (no gate having more than 4 inputs). Especially compact and efficient is the pipelined implementation (Fig. 45-1 (c)), which can produce the sum at a rate of 3-gate delays/bit. The high-speed adder circuits can be used on gate arrays or full-custom ICs to implement fast calculation of addresses or data values. Because of their compact nature, they also use less space on the silicon than conventional adders do.




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