S1Ngle-Ic Logic Probe

  
This logic probe uses a CD4009 CMOS hex inverter. The characteristic high-input impedance of CMOS gives the advantage
S1Ngle-Ic Logic Probe - schematic

of not loading the circuit being tested. Because the output of the inverters is not specified at either a high or low level with a floating input, an input-bias network produces lows at both input inverter pairs if the input is open or at less than 2 V. Resistor R3 holds the input of inverter 3 low which makes the output of inverters 4 and 5 low and will not permit LED 2 to light. At the same time, Rl holds the inputs of inverters 1 and 2 high so that their output is low and LED 1 will not light. If the probe input is touched to a logic low, the output of inverter 3 is held high by R3 and inverter 1 and 2 are brought low, which causes their outputs to go high and turns on LED 1. With no input, both LEDs should be off.




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