8-Digit up-down counter

This circuit shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b is active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked.

the Q output of the flip flop goes high and turns on the npn transistor, thereby inhibiting leading zero blanking on the low order counter.

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